Thin film transistor array panel for a display device and a method of manufacturing the same

ABSTRACT

A method of manufacturing a thin film transistor array panel includes forming gate lines including gate electrodes on an insulation substrate; forming a gate insulating layer, semiconductor layer, and etch stop layer on the gate lines; etching and patterning the etch stop and semiconductor layers at the same time using photolithography; ashing and partially removing a photoresist film pattern used in the patterning of the etch stop and semiconductor layers; etching the etch stop layer exposed by removed portions of the photoresist film pattern to form etch stop members; depositing ohmic contact and data metal layers onto the etch stop members, etching the ohmic contact and data metal layers at the same time using photolithography to form data lines having source and drain electrodes, and ohmic contact members below the source and drain electrodes; forming a passivation layer on the data lines and drain electrodes; and forming pixel electrodes on the passivation layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No.10-2006-0036719 filed in the Korean Intellectual Property Office on Apr.24, 2006, the disclosure of which is incorporated by reference herein inits entirety.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a thin film transistor array panel fora display device and a method of manufacturing the same.

2. Discussion of the Related Art

Liquid crystal displays are among the most widely used flat paneldisplays. For example, flat panel liquid crystal displays are commonlyfound in a variety of electronic devices such as televisions, laptopcomputers, personal digital assistants, cell phones and digital cameras.

A liquid crystal display has two substrates on which electrodes areformed, and a liquid crystal layer interposed between the substrates.The liquid crystal display is a display device in which a voltage isapplied to the electrodes to rearrange liquid crystal molecules in theliquid crystal layer to control the amount of light passing through thesubstrates.

A liquid crystal display having field generating electrodes respectivelyprovided on two display panels is now widely used. In thisconfiguration, a plurality of pixel electrodes are arranged on a displaypanel in a matrix shape, and a common electrode covers the entiresurface of the other display panel. In such a liquid crystal display, anadditional voltage is applied to the pixel electrodes to perform imagedisplay. To accomplish this, thin film transistors, which arethree-terminal elements, are respectively connected to the pixelelectrodes to switch the voltage to be applied to the pixel electrodes.Further, gate lines that transmit signals for controlling the thin filmtransistors and data lines that transmit the voltage to be applied tothe pixel electrodes are formed on the display panel.

Each of the thin film transistors functions as a switching element thattransmits or blocks an image signal to be transmitted through the dataline to the pixel electrode, depending on a scanning signal that istransmitted through the gate line. Each of the thin film transistorsalso functions as a switching element that individually controls alight-emitting device, for example, in an Active Matrix OrganicLight-Emitting Device (AM-OLED).

SUMMARY OF THE INVENTION

Such thin film transistors are classified into a bottom gate type and atop gate type according to the structures. The bottom gate type isfurther classified into an etch back type and an etch stopper type. Thebottom gate type is mainly applied to a thin film transistor using asemiconductor formed of amorphous silicon. For the etch back type ofthin film transistor, the manufacturing process is relatively simplecompared with the etch stopper type, but reliability and charge mobilityare low. Meanwhile, the etch stopper type has excellent reliability andcharge mobility compared with the etch back type. However, in the etchstopper type, an additional manufacturing process is required to form anetch stopper.

Embodiments of the present invention have been made in an effort toprovide a thin film transistor array panel for a display device and amethod of manufacturing the same, having advantages of simplifying amanufacturing process of an etch stopper type of thin film transistorarray panel.

According to an exemplary embodiment of the present invention, a thinfilm transistor array panel includes an insulation substrate, gate linesthat are formed on the insulation substrate and that have gateelectrodes, a gate insulating layer that is formed on the gate lines,semiconductors that are formed on the gate insulating layer, etch stopmembers that are formed on portions of the semiconductors, ohmic contactmembers that are formed on the etch stop members and that partiallycontact the semiconductors, a data wire layer that is formed on theohmic contact members and that has substantially the same planar patternas that of the ohmic contact members, a passivation layer that is formedon the data wire layer and that has contact holes, and pixel electrodesthat are formed on the passivation layer and that are connected toportions of the data wire layer through the contact holes.

The data wire layer may have data lines that have source electrodes andintersect the gate lines, drain electrodes that are disposed on the gateelectrodes and face the source electrodes, and storage capacitorconductors that overlap the gate lines.

Each of the semiconductors may have a linear portion that is formedbelow a corresponding data line and a protruding portion that extendsfrom the linear portion over a corresponding source electrode and drainelectrode. Each of the etch stop members may have a protruding portionthat is formed on the protruding portion of a correspondingsemiconductor to cover the corresponding semiconductor located betweenthe corresponding source electrode and drain electrode.

Each of the etch stop members may further have a linear portion that isformed on the linear portion of the corresponding semiconductor and thatmay be located within an area defined by sides of the linear portion ofthe corresponding semiconductor. The protruding portion of the etch stopmembers may be located within an area defined by sides of the protrudingportion of the corresponding semiconductor.

Each of the semiconductors may be formed of amorphous silicon, and eachof the etch stop members may be formed of silicon nitride.

According to an exemplary embodiment of the present invention, a methodof manufacturing a thin film transistor array panel includes forminggate lines having gate electrodes on an insulation substrate; forming agate insulating layer, a semiconductor layer, and an etch stop layer onthe gate lines; etching and patterning the etch stop layer andsemiconductor layer at the same time using photolithography; ashing andpartially removing a photoresist film pattern used in the etching andpatterning of the etch stop layer and the semiconductor layer; etchingthe etch stop layer exposed by removed portions of the photoresist filmpattern to form etch stop members; depositing an ohmic contact layer anda data metal layer onto the etch stop members; etching the ohmic contactlayer and the data metal layer at the same time using photolithographyto form data lines having source electrodes, drain electrodes facing thesource electrodes, and ohmic contact members below the source electrodesand the drain electrodes; forming a passivation layer on the data linesand the drain electrodes; and forming pixel electrodes on thepassivation layer.

Each of the ohmic contact members may be formed to have substantiallythe same planar pattern as that of a data line and drain electrodeformed thereon.

The method may further include connecting the pixel electrodes to thedrain electrodes. The gate insulating layer, semiconductor layer, andetch stop layer may he sequentially formed on the gate lines.

According to an exemplary embodiment of the present invention, a thinfilm transistor array panel includes an insulation substrate; gate linesthat are formed on the insulation substrate and that have first gateelectrodes, second gate electrodes, and storage electrodes that areformed on the insulation substrate; a gate insulating layer that isformed on the gate lines, the second gate electrodes, and the storageelectrodes; first and second semiconductors that are formed on the gateinsulating layer; first and second etch stop members that are formed onportions of the first and second semiconductors, respectively; ohmiccontact members that are formed on the first and second etch stopmembers and that partially contact the semiconductors; a data wire layerthat is formed on the ohmic contact member and that has substantiallythe same planar pattern as that of the ohmic contact members; apassivation layer that is formed on the data wire layer and that has aplurality of contact holes; and pixel electrodes that are formed on thepassivation layer and that are connected to portions of the data wirelayer through the contact holes.

The data wire layer may have data lines that have first sourceelectrodes and intersect the gate lines, first drain electrodes that aredisposed on the first gate electrodes and face the first sourceelectrodes, power lines that have second source electrodes and intersectthe gate lines, arid second drain electrodes that are disposed on thesecond gate electrodes and face the second source electrodes. The thinfilm transistor array panel may further include connecting members thatelectrically connect the first drain electrodes and the second gateelectrodes to each other.

Each of the first semiconductors may have a linear portion that isformed below a corresponding data line, and a first channel portion thatextends from the linear portion over a corresponding first sourceelectrode and first drain electrode. Each of the second semiconductorsmay have a storage electrode portion that overlaps a correspondingstorage electrode, and a second channel portion that extends over acorresponding second source electrode and second drain electrode. Eachof the first etch stop members may cover the first semiconductor betweenthe corresponding first source electrode and first drain electrode. Eachof the second etch stop members may cover the second semiconductorbetween the corresponding second source electrode and second drainelectrode.

The first and second semiconductors may be formed of amorphous silicon,and the first and second etch stop members may be formed of siliconnitride.

The thin film transistor array panel may further include partition wallsthat are formed on the pixel electrodes, a light emission layer thatfills frames defined by the partition walls, and a common electrode thatis formed on the light emission layer.

According to an exemplary embodiment of the present invention, a methodof manufacturing a thin film transistor array panel includes forminggate lines having first gate electrodes, second gate electrodes, andstorage electrodes on an insulation substrate; forming a gate insulatinglayer, a semiconductor layer, and an etch stop layer on the gate lines,the second gate electrodes, and the storage electrodes; etching andpatterning the etch stop layer and the semiconductor layer at the sametime using photolithography; ashing and partially removing a photoresistfilm pattern used in the etching and patterning of the etch stop layerand the semiconductor layer; etching the etch stop layer exposed byremoved portions of the photoresist film pattern to form first andsecond etch stop members; depositing an ohmic contact layer and a datametal layer onto the first and second etch stop members; etching theohmic contact layer and the data metal layer at the same time usingphotolithography to form data lines having first source electrodes,drain electrodes facing the first source electrodes, power lines havingsecond source electrodes, second drain electrodes facing the secondsource electrodes, and ohmic contact members below the drain electrodes;forming a passivation layer on the data lines, the first drainelectrodes, the power lines, and the second drain electrodes; andforming pixel electrodes on the passivation layer that are connected tothe second drain electrodes and connecting members electricallyconnecting the first drain electrodes and second gate electrodes to eachother.

Each of the ohmic contact members may be formed to have substantiallythe same pattern as that of a corresponding data line, first drainelectrode, power line, and second drain electrode formed thereon.

The method may further include forming partition walls on the pixelelectrodes, forming an organic light emission layer that fills framesdefined by the partition walls, and forming a common electrode on theorganic light emission layer.

The gate insulating layer, semiconductor layer, and etch stop layer maybe sequentially formed on the gate lines, the second gate electrodes,and the storage electrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a layout view of a thin film transistor array panel accordingto an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panelof FIG. 1 taken along line II-II′.

FIG. 3A, FIG. 4A, FIG. 5A, FIG. 6A, and FIG. 7A are layout views of thethin film transistor array panel shown in FIGS. 1 and 2 during amanufacturing process thereof according to an exemplary embodiment ofthe present invention.

FIG. 3B is a cross-sectional view taken along line IIIb-IIIb′ of FIG.3A.

FIG. 4B is a cross-sectional view taken along line IVb-IVb′ of FIG. 4A.

FIG. 5B is a cross-sectional view taken along line Vb-Vb′ of FIG. 5A.

FIG. 6B is a cross-sectional view taken along line VIb-VIb′ of FIG. 6A.

FIG. 7B is a cross-sectional view taken along line VIIb-VIIb′ of FIG.7A.

FIG. 8 is a layout view showing an organic light-emitting display deviceaccording to an exemplary embodiment of the present invention.

FIG. 9A and FIG. 9B are cross-sectional views of a thin film transistorarray panel of FIG, 8 taken along lines IXa-IXa′ and IXb-IXb′,respectively.

FIG. 10, FIG. 12, FIG. 14, and FIG. 16 are layout views of the organiclight-emitting display device of FIG. 8 during a manufacturing processthereof according to an exemplary embodiment of the present invention.

FIG. 11A is a cross-sectional view taken along line XIa-XIa′ of FIG. 10.

FIG. 11B is a cross-sectional view taken along line XIb-XIb′ of FIG. 10.

FIG. 13A is a cross-sectional view taken along line XIIIa-XIIIa′ of FIG.12.

FIG. 13B is a cross-sectional view taken along line XIIIb-XIIIb′ of FIG.12.

FIG. 15A is a cross-sectional view taken along line XVa-XVa′ of FIG. 14.

FIG. 15B is a cross-sectional view taken along line XVb-XVb′ of FIG. 14.

FIG. 17A is a cross-sectional view taken along line XVIIa-XVIIa′ of FIG.16.

FIG. 17B is a cross-sectional view taken along line XVIIb-XVIIb′ of FIG.16.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

The present invention will be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. In the drawings, the thickness oflayers, films, panels, regions, etc., are exaggerated for clarity. Likereference numerals designate like elements throughout the specification.It will be understood that when an element such as a layer, film,region, or substrate is referred to as being “on” another element, itcan be directly on the other element or intervening elements may also bepresent. In contrast, when an element is referred to as being “directlyon” another element, there are no intervening elements present.

A thin film transistor array panel according to an exemplary embodimentof the present invention will be described in detail with reference toFIGS. 1 and 2.

FIG. 1 is a layout view of a thin film transistor array panel accordingto an exemplary embodiment of the present invention, and FIG. 2 is across-sectional view of the thin film transistor array panel of FIG. 1taken along line II-II′.

As shown in FIGS. 1 and 2, a plurality of gate lines 121 that transmitgate signals are formed on an insulation substrate 110 formed oftransparent glass or the like. The gate lines 121 extend in a horizontaldirection and portions of the gate lines 121 form a plurality of gateelectrodes 124. Other portions of the gate lines 121 protrude downwardand form a plurality of expansions 127, and still other portions of thegate lines 121 form ends 129 for connection to an external circuit.

A gate electrode 124, a source electrode 173, and a drain electrode 175form a thin film transistor, together with a protruding portion 154 of asemiconductor stripe 151. A channel of the thin film transistor isformed at the protruding portion 154 between the source electrode 173and the drain electrode 175. A storage capacitor conductor 177 overlapsthe expansion 127 of the gate line 121.

Each of the gate lines 121 may be formed of an aluminum-based metal suchas aluminum. (Al) or an aluminum alloy, a silver-based metal such assilver (Ag) or a silver alloy, a copper-based metal such as copper (Cu)or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or amolybdenum alloy, chromium (Cr), tantalum (Ta), titanium (Ti), or thelike. However, the gate lines 121 may have a multilayer structure havingtwo conductive layers (not shown) with different physical properties.One conductive layer is formed of a metal with low resistivity, forexample an aluminum-based metal, a silver-based metal, and acopper-based metal to reduce a signal delay or voltage drop. On theother hand, the other conductive layer is formed of a differentmaterial, particularly a material with excellent physical, chemical, andelectrical contact characteristics to Indium Tin Oxide (ITO) and IndiumZinc Oxide (IZO), for example a molybdenum-based metal, chromium,tantalum, titanium, or the like. An exemplary multi-layered structuremay include a chromium lower layer and an aluminum (alloy) upper layeror an aluminum (alloy) lower layer and a molybdenum (alloy) upper layer.

A side of the gate line 121 is inclined at an angle of about 30 to about80 degrees with respect to a surface of the substrate 110.

A gate insulating layer 140 formed of silicon nitride (SiN_(x)) or thelike is formed on the gate line 121.

A plurality of semiconductor stripes 151 formed of hydrogenatedamorphous silicon or the like are formed on the gate insulating layer140. Each of the semiconductor stripes 151 extends in a verticaldirection, and a plurality of protruding portions 154 protrude from thesemiconductor stripe 151 toward the gate electrode 124. In addition, thesemiconductor stripe 151 has a larger width where the semiconductorstripe 151 meets the gate line 121.

Etch stop members 112 and 113 formed of silicon nitride (SiN_(x)) areformed on the semiconductor stripe 151. Each of the etch stop members112 and 113 includes a linear portion 113 that is formed along thesemiconductor stripe 151, and a protruding portion 112 that is formed onthe protruding portion 154 of the semiconductor stripe 151. Each of theetch stop members 112 and 113 has a width smaller than that of theprotruding portion 154 and the semiconductor stripe 151, respectively,and a distance from a side of the protruding portion 154 to a side ofthe etch stop member 112 is substantially the same at all points on aperimeter of the etch stop member 112 and a distance from a side of thesemiconductor stripe 151 to a side of the etch stop member 113 issubstantially the same at all points on a perimeter of the etch stopmember 113. The etch stop members 112 and 113 are disposed in an areadefined by the sides of the semiconductor stripe 151 and the protrudingportion 154.

A plurality of ohmic contact stripes and islands 161 and 165 formed of amaterial such as n+ hydrogenated amorphous silicon doped with an n-typeimpurity at a high concentration are formed on the etch stop members 112and 113. Each of the ohmic contact stripes 161 has a plurality ofprotruding portions 163, and each of the protruding portions 163 andeach of the ohmic contact islands 165 are disposed in a pair on theprotruding portion 154 of the semiconductor stripe 151. The protrudingportion 163 of the ohmic contact stripe 161 and the ohmic contact island165 are in contact with the protruding portion 154 of the semiconductorstripe 151, which is not covered with the protruding portion 112 of theetch stop member. Since the ohmic contact stripe 161 has a larger widththan that of the semiconductor stripe 151, it covers the semiconductorstripe 151, excluding the protruding portion 154 of the semiconductorstripe 151. However, the width of the ohmic contact stripe 161 may bethe same as that of the semiconductor stripe 151.

A plurality of data lines 171, a plurality of the drain electrodes 175,and a plurality of the storage capacitor conductors 177 are formed onthe ohmic contact members 161, 163 and 165, and ohmic contact member167.

The data lines 171 extend in the vertical direction to intersect thegate lines 121, and transmit a data voltage. A plurality of branchesthat extend from each of the data lines 171 toward the drain electrode175 form the source electrodes 173. A source electrode 173 and drainelectrode 175 are separated from each other and are disposed on opposingsides with respect to the gate electrode 124.

The planar shape of the data line 171 having the source electrode 173,the drain electrode 175, and the storage capacitor conductor 177 issubstantially the same as the ohmic contact stripe 161 and ohmic contactisland 165. This is because the ohmic contact members 161 and 165, thedata line 171, the drain electrode 175 and the storage capacitorconductor 177, are simultaneously etched and patterned using onephotolithography process.

The data line 171, the drain electrode 175, and the storage capacitorconductor 177 may be formed of a refractory metal such as molybdenum,chromium, tantalum, or titanium, or an alloy thereof, and may have amultilayer structure having a refractory metal film (not shown) and alow-resistance conductive layer (not shown). Exemplary multi-layeredstructures may include a two-layered film of a chromium or molybdenum(alloy) lower layer and an aluminum (alloy) upper layer, and athree-layered film of a molybdenum (alloy) lower layer, an aluminum(alloy) intermediate layer, and a molybdenum (alloy) upper layer. Thedata line 171, the drain electrode 175, and the storage capacitorconductor 177, however, may be formed of various metals or conductors inaddition to the above-mentioned materials.

Sides of the data line 171, the drain electrode 175, and the storagecapacitor conductor 177 are formed to have an inclined angle of about 30to about 80 degrees.

The ohmic contact members 161 and 165 are disposed between theunderlying semiconductor layer 154 and the overlying source electrode173 and drain electrode 175, and function to reduce contact resistance.

A portion of the protruding portion 112 of the etch stop member betweenthe source electrode 173 and drain electrode 175 remains exposed, notcovered with the data line 171 and the drain electrode 175.

A passivation layer 180 formed of an organic material with an excellentplanarization characteristic and photosensitivity, a low-dielectricconstant insulating material such as a-Si:C:O and a-Si:O:F formed byPlasma Enhanced Chemical Vapor Deposition (PECVD), or an inorganicmaterial such as silicon nitride (SiN_(x)) or the like is formed on thedata line 171, the drain electrode 175, the storage capacitor conductor177, and the exposed semiconductor stripe 151 in a single layer ormultiple layers.

A plurality of contact holes 185, 187, and 182, which expose the drainelectrode 175, the storage capacitor conductor 177, and an end 179 ofthe data line 171, respectively, are formed in the passivation layer180. Further, a contact hole 181 is formed to pass through thepassivation layer 180 and the gate insulating layer 140 to expose theend 129 of the gate line 121.

A plurality of pixel electrodes 190 and contact assistants 81 and 82formed of ITO or IZO are formed on the passivation layer 180.

The pixel electrode 190 is physically and chemically connected to thedrain electrode 175, the storage capacitor conductor 177, and the dataline 171 through the contact holes 185 and 187. The pixel electrode 190is supplied with the data voltage from the drain electrode 175 andtransmits the data voltage to the storage capacitor conductor 177.

The pixel, electrode 190 with the applied data voltage generates anelectric field together with a common electrode (not shown) of anotherdisplay panel (not shown) with an applied common voltage, and rearrangesliquid crystal molecules of a liquid crystal layer interposedtherebetween.

The pixel electrode 190 and common electrode (not shown) form a liquidcrystal capacitor and hold the applied voltage even when the thin filmtransistor is turned off. An additional capacitor (referred to as a“storage capacitor”) is coupled in parallel to the liquid crystalcapacitor and is provided to enhance the voltage holding capacity of theliquid crystal capacitor. The storage capacitor may be formed byoverlapping the pixel electrode 190 and an adjacent gate line 121(referred to as a “previous gate line”). To increase electrostaticcapacitance, for example, storage capacitance of the storage capacitor,an expansion 127 formed by expanding the gate line 121 is provided toincrease the area of the gate line 121 overlapped by the storagecapacitor conductor 177. Further, the storage capacitor conductor 177that is connected to the pixel electrode 190 and overlaps the expansion127 is disposed below the passivation layer 180 to reduce a distancebetween the pixel electrode 190 and the expansion 127.

Meanwhile, a separate storage electrode line may be formed and overlapthe pixel electrode 190, instead of overlapping the previous gate line121 and the pixel electrode 190 to form the storage capacitor.

When the passivation layer 180 is formed of an organic material having alow dielectric constant, an aperture ratio may be increased byoverlapping the pixel electrode 190, and the adjacent gate line 121 anddata line 171.

The contact assistants 81 and 82 are connected to the ends 129 and 179of the gate line 121 and the data line 171 through the contact holes 181and 182, respectively. The contact assistants 81 and 82 complementadhesion of the ends 129 and 179 of the gate line 121 and data line 171,respectively, to an external device, such as a driver IC, and protectthem.

A method of manufacturing the thin film transistor array panel shown inFIGS. 1 and 2 according to an exemplary embodiment of the presentinvention will now be described in detail with reference to FIGS. 3A to7B.

FIG, 3A, FIG. 4A, FIG. 5A, FIG. 6A and FIG. 7A are layout views of thethin film transistor array panel shown in FIGS. 1 and 2 during amanufacturing process thereof according to the exemplary embodiment ofthe present invention, FIG. 3B is a cross-sectional view taken alongline IIIb-IIIb′ of FIG. 3A, FIG. 4B is a cross-sectional view takenalong line IVb-IVb′ of FIG. 4A, FIG. 5B is a cross-sectional view takenalong line Vb-Vb′ of FIG. 5A, FIG. 6B is a cross-sectional view takenalong line VIb-VIb′ of FIG. 6A and FIG. 7B is a cross-sectional viewtaken along line VIIb-VIIb′ of FIG. 7A.

As shown in FIGS. 3A and 3B, a gate metal layer formed of aluminum (Al)or an aluminum alloy is deposited on the insulation substrate 110 formedof transparent glass. The gate lines 121 having the plurality of gateelectrodes 124, the expansions 127, and the ends 129 for connection toan external circuit are formed by etching the gate metal layer usingphotolithography. Each of the gate lines 121 may have a two-layeredstructure of chromium and aluminum. In this case, the chromium andaluminum layers may have thicknesses of about 500 Å and about 2500 Å,respectively.

As shown in FIGS. 4A and 4B, the gate insulating layer 140 is formed bydepositing silicon nitride (SiN_(x)) or silicon oxide (SiO₂) to coverthe gate lines 121 having the gate electrodes 124. An intrinsicamorphous silicon layer and an etch stop layer formed of silicon nitrideor the like are sequentially deposited on the gate insulating layer 140.The semiconductor stripes 151 having the plurality of protrudingportions 154 and pre-patterns 116 of the etch stop members 112 and 113are formed by etching the etch stop layer and the intrinsic amorphoussilicon layer using photolithography. The gate insulating layer 140, theamorphous silicon layer, and the etch stop layer may have thicknesses ofabout 4500 Å, about 500 Å, and about 1500 Å, respectively. Moreover, thegate insulating layer 140 may have a two-layered structure of siliconoxide (SiO₂) and silicon nitride. In this case, the silicon oxide layerand the silicon nitride layer may have thicknesses of about 1500 Å andabout 2000 Å, respectively. Reference symbol PR in FIG. 4B denotes aphotoresist film used in the photolithography.

As shown in FIGS. 5A and 5B, if a portion of the photoresist film PR isremoved by ashing, the photoresist film PR is reduced in thickness andin width, and thus, the pre-patterns 116 of the etch stop members 112and 113 are partially exposed. The etch stop members 112 and 113 arecompleted by etching the pre-patterns 116. Here, the amount of ashing ofthe photoresist film PR is adjusted according to the width of each ofthe etch stop members 112 and 113 to be formed. If the photoresist filmPR is excessively ashed, the linear portion 113 of the etch stop members112 and 113 may not be formed. The remaining photoresist film PR isremoved.

As shown in FIGS. 6A and 6B, a material such as n+ hydrogenatedamorphous silicon, in which an n-type impurity is doped at a highconcentration, is deposited on the etch stop members 112 and 113 to forman ohmic contact layer. A data metal layer formed of a refractory metalsuch as molybdenum, chromium, tantalum, or titanium, or an alloythereof, is deposited on the ohmic contact layer. The ohmic contactlayer and the data metal layer may thicknesses of about 500 Å and about1500 Å, respectively. The ohmic contact members 161 and 165, the datalines 171, the drain electrodes 175, and the storage capacitorconductors 177 are formed by etching the data metal layer and the ohmiccontact layer at the same time using photolithography.

As shown in FIG. 6B, a plurality of the ohmic contact stripes 161 eachhaving a plurality of the protruding portions 163, and a plurality ofohmic the contact islands 165 and 167 are formed.

As shown in FIGS. 7A and 7B, the passivation layer 180 is formed byforming an organic material with a desired planarization characteristicand photosensitivity, a low-dielectric constant insulating material suchas a-Si:C:O and a-Si:O:F formed by PECVD, or an inorganic material suchas silicon nitride (SiN_(x)), in a single layer or multiple layers. Whenthe passivation layer 180 is formed of silicon nitride, the thicknessthereof may be about 2000 Å.

The plurality of contact holes 181, 185, 187, and 182 are formed byetching the passivation layer 180 and the gate insulating layer 140using photolithography.

As shown in FIGS. 1 and 2, ITO or IZO is deposited on the substrate 110by sputtering to form the plurality of pixel electrodes 190 and thecontact assistants 81 and 82 using photolithography.

Hereinafter, a thin film transistor array panel for an organiclight-emitting display device according to an exemplary embodiment ofthe present invention will be described in detail with reference toFIGS. 8 to 17B.

FIG. 8 is a layout view of an organic light-emitting display deviceaccording to an exemplary embodiment of the present invention, and FIGS.9A and 9B are cross-sectional views of a thin film transistor arraypanel of FIG. 8 taken along lines IXa-IXa′ and IXb-IXb′, respectively,

A plurality of gate lines 121 that transmit gate signals are formed onan insulation substrate 110 formed of glass. The gate lines 121 extendin the horizontal direction, and part of each, of the gate lines 121protrude therefrom and form a plurality of first gate electrodes 124 a.Second gate electrodes 124 b are formed in the same layer as the gatelines 121. Storage electrodes 133 that extend in the vertical directionare respectively connected to the second gate electrodes 124 b.

Sides of the gate lines 121 and the storage electrodes 133 are inclinedat an angle of about 30 to about 80 degrees with respect to thesubstrate 110.

A gate insulating layer 140 formed of silicon nitride (SiN_(x)) or thelike is formed on the gate lines 121. The gate insulating layer 140 mayhe formed in a two-layered structure of silicon oxide and siliconnitride.

A plurality of semiconductor stripes 151 and semiconductor islands 154 bformed of hydrogenated amorphous silicon or the like are formed on thegate insulating layer 140. The semiconductor stripes 151 extend in thevertical direction, and a plurality of protruding portions 154 aprotrude from each of the semiconductor stripes 151 toward the firstgate electrodes 124 a and form first channel portions overlapping thefirst gate electrode 124 a. In addition, each of the semiconductorstripes 151 has a larger width where the semiconductor stripe 151 meetsthe gate line 121. Each of the semiconductor islands 154 b has a secondchannel portion that intersects the second gate electrode 124 b, and astorage electrode portion 157 that overlaps the storage electrode 133.

Etch stop members 114 and 115 formed of silicon nitride (SiN_(x)) or thelike are formed on the semiconductor stripe 151 and the semiconductorisland 154 b. The etch stop members 114 and 115 include a first etchstop member 114 that is formed on the protruding portion 154 a of thesemiconductor stripe 151 and a second etch stop member 115 that isformed on the semiconductor island 154 b. The etch, stop members 114 and115 have a width smaller than that of the protruding portion 154 a ofthe semiconductor stripe 151 and the semiconductor island 154 b,respectively. A distance from a side of the protruding portion 154 a ofthe semiconductor stripe 151 to a side of the etch stop member 114 issubstantially the same along a perimeter of the etch stop member 114 anda distance from a side of the semiconductor island 154 b to a side ofthe etch stop member 115 is substantially the same along a perimeter ofthe etch stop member 115.

A plurality of ohmic contact stripes and islands 161, 165 a, 163 b, 165b and 167 formed of a material such as n+ hydrogenated amorphous siliconin which an n-type impurity is doped at a high concentration are formedon the etch stop members 114 and 115. Each of the ohmic contact stripes161 has a plurality of protruding portions 163 a. Each of the protrudingportions 163 a and each of the ohmic contact islands 165 a are disposedin a pair on the protruding portion 154 a of the semiconductor stripe151. In addition, each of the protruding portions 163 b and each of theohmic contact islands 165 b face each other in a pair, centered on thesecond gate electrode 124 b, and are disposed on the semiconductorisland 154 b. The protruding portion 163 a and the ohmic contact island165 a are in contact with the protruding portion 154 a of thesemiconductor stripe 151 not covered with the first etch stop member114. The protruding portion 163 b and the ohmic contact island 165 b arein contact with the semiconductor island 154 b not covered with thesecond etch stop member 115.

A plurality of data lines 171, first drain electrodes 175 a, power lines172, and second drain electrodes 175 b are formed on the ohmic contactstripes and islands 161, 165 a, 163 b, and 165 b, respectively.

The data lines 171 and the power lines 172 extend in the verticaldirection to intersect the gate lines 121, and transmit a data voltageand a source voltage, respectively. A plurality of branches that extendfrom each of the data lines 171 toward the first drain electrodes 175 aform first source electrodes 173 a. In addition, a plurality of branchesthat extend from each of the power lines 172 toward the second drainelectrodes 175 b form second source electrodes 173 b. A pair of thefirst and second source electrodes 173 a and 173 b and a pair of thefirst and second drain electrodes 175 a and 175 b are separated fromeach other and are disposed on opposite sides with respect to the firstand second gate electrodes 124 a and 124 b, respectively.

The planar shapes of the data line 171, the first drain electrode 175 a,the power line 172, and the second drain electrode 175 b aresubstantially the same as those of the ohmic contact stripes and islands161, 165 a, 163 b, and 165 b therebelow. This is because the ohmiccontact members 161, 165 a, 163 b, and 165 b, and the data Sine 171, thefirst drain electrode 175 a, the power line 172, and second drainelectrode 175 b, are patterned at the same time using a photolithographyprocess.

The first gate electrode 124 a, the first source electrode 173 a, andthe first drain electrode 175 a form a switching thin film transistor,together with the protruding portion 154 a of the semiconductor stripe151. In addition, the second gate electrode 124 b, the second sourceelectrode 173 b, and the second drain electrode 175 b form a drivingthin film transistor, together with the semiconductor island 154 b, Atthis time, the power line 172 overlaps the storage electrode portion 157of the semiconductor island 154 b.

Sides of the data Sine 171, the first and second drain electrodes 175 aand 175 b, and the power line 172 are inclined at an angle of about 30to about 80 degrees.

The ohmic contact stripes and islands 161, 163 b, 165 a, and 165 b arerespectively disposed between the semiconductor stripe 151 andsemiconductor island 154 b, and the overlying data line 171, first drainelectrodes 175 a and 175 b, and power line 172 to reduce contactresistance.

The first etch stop member 114 has an exposed portion not covered withthe data line 171 and the first drain electrode 175 a between the firstsource electrode 173 a and first drain electrode 175 a, and the secondetch stop member 115 has an exposed portion not covered with the powerline 172 and the second drain electrode 175 b between the second sourceelectrode 173 b and the second drain electrode 175 b.

A passivation layer 180 formed of an inorganic insulating layer such assilicon nitride, an organic material having an excellent planarizationcharacteristic and photosensitivity, or a low-dielectric constantinsulating material such as a-Si:C:O and a-Si:O:F formed by PECVD, isformed on the data line 171, the first and second drain electrodes 175 aand 175 b, the power line 172, and the exposed portions of thesemiconductor stripe 151 and semiconductor island 154 b.

A plurality of contact holes 181, 185, and 182, which expose the firstdrain electrode 175 a, the second drain electrode 175 b, and an end 179of the data line 171, respectively, are formed in the passivation layer180. In addition, a plurality of contact holes 183 and 189, which exposethe second gate electrode 124 b and an end 129 of the gate line 121,respectively, are formed in the passivation layer 180 and gateinsulating layer 140.

A plurality of pixel electrodes 190, connecting members 192, and contactassistants 81 and 82, all of which are formed of ITO or IZO, are formedon the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to thesecond drain electrode 175 b through the contact hole 185, and theconnecting member 192 connects the first drain electrode 175 a and thesecond gate electrode 124 b through the contact holes 181 and 183. Thecontact assistants 81 and 82 are connected to the ends 129 and 179 ofthe gate line 121 and the data line 171 through the contact holes 189and 182, respectively.

Partition wails 803 formed of an organic or inorganic insulatingmaterial are formed on the passivation layer 180 to separate organiclight emission cells from one another. Each of the partition walls 803surrounds the edges of the pixel electrode 190 and defines a region tobe filled with an organic light emission layer 70.

The light emission layer 70 is formed on the region surrounded by thepartition wall 803 on the pixel electrode 190. The light emission layer70 is formed of an organic material emitting one of red (R), green (G),and blue (B) colors. The light emitting materials for the red (R), green(G), and blue (B) colors are sequentially and repeatedly disposed.

Alternatively, the light emission layer 70 may be formed on a holeinjection layer (not shown) after the hole injection layer is formed ina region on the pixel electrode 190 surrounded by the partition wall803. The hole injection layer may be formed ofpoly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) (PEDOT/PSS).

An auxiliary electrode 272, which has the same pattern as the partitionwall 803 and is formed of a conductive material having low resistivity,is formed on the partition wall 803. The auxiliary electrode 272 is incontact with a common electrode 270 to be formed later, and reducesresistance of the common electrode 270.

The common electrode 270 is formed on the partition wall 803, the lightemission layer 70, and the auxiliary electrode 272. The common electrode270 is formed of a metal, such as aluminum (Al), having low resistance.A bottom emission type organic light-emitting display device has beendescribed in accordance with an exemplary embodiment of the presentinvention. However, in a front emission type or a both-side emissiontype organic light-emitting display device, the common electrode 270 maybe formed of a transparent conductive material, such as ITO or IZO.

A method of manufacturing the organic light-emitting display deviceshown in FIGS. 8 to 9B will be described in detail with reference toFIGS. 10 to 17B.

FIG. 10, FIG. 12, FIG. 14, and FIG. 16 are layout views of the organiclight-emitting display device of FIG. 8 during a manufacturing processthereof according to an exemplary embodiment of the present invention,FIG. 11A is a cross-sectional view taken along line XIa-XIa′ of FIG. 10,FIG. 11B is a cross-sectional view taken along line XIb-XIb′ of FIG. 10,FIG. 13A is a cross-sectional view taken along Sine XIIIa-XIIIa′ of FIG.12, FIG. 13B is a cross-sectional view taken along line XIIIb-XIIIb′ ofFIG. 12, FIG. 15A is a cross-sectional view taken along line XVa-XVa′ ofFIG. 14, FIG. 15B is a cross-sectional view taken along line XVb-XVb′ ofFIG. 14, FIG. 17A is a cross-sectional view taken along lineXVIIa-XVIIa′ of FIG. 16, and FIG. 17B is a cross-sectional view takenalong line XVIIb-XVIIb′ of FIG. 16.

As shown in FIGS. 10 to 11B, a gate metal layer formed of aluminum (Al)or an aluminum alloy is deposited on the insulation substrate 110 formedof transparent glass or plastic. The gate lines 121 having the firstgate electrodes 124 a, second gate electrodes 124 b, and storageelectrodes 133 are formed by etching the gate metal layer usingphotolithography. The gate line 121, the second gate electrode 124 b,and the storage electrode 133 may be formed in a two-layered structureof chromium and aluminum. In this case, the chromium and aluminum layersmay have thicknesses of about 500 Å and about 2500 Å, respectively.

As shown in FIGS. 12 to 13B, the gate insulating layer 140 is formed bydepositing silicon nitride (SiN_(x)) or silicon oxide (SiO₂). Anintrinsic amorphous silicon layer and an etch stop layer formed ofsilicon nitride are successively deposited. The semiconductor stripes151 and semiconductor islands 154 b, which have a plurality ofprepatterns 117 of the etch stop members 114 and 115 and protrudingportions 154 a, respectively, are formed by etching the etch stop layerand the intrinsic amorphous silicon layer using photolithography. Thegate insulating layer 140 may be formed of silicon nitride (SiN_(x)),and a deposition temperature may be about 250 to about 500° C. Moreover,the thickness thereof may be about 2000 to about 5000 Å. Referencesymbol PR in FIGS. 13A and 13B denotes a photoresist film used in thephotolithography.

As shown in FIGS. 14 to 15B, if a portion of the photoresist film PR isremoved by ashing, the photoresist film PR is reduced in thickness andwidth, and thus, the pre-pattern 117 of etch stop members 114 and 115 ispartially exposed. The etch stop members 114 and 115 are completed byetching the exposed pre-pattern 117. The photoresist film PR is removed.

As shown in FIGS. 16 to 17B, an ohmic contact layer is formed bydepositing a material such as n+ hydrogenated amorphous silicon, inwhich an n-type impurity is doped at a high concentration, on the etchstop members 114 and 115. In addition, a data metal layer formed of arefractory metal such as molybdenum, chromium, tantalum, or titanium, oran alloy thereof, is deposited on the ohmic contact layer. Here, theohmic contact layer and the data, metal layer may have thicknesses ofabout 500 Å and about 1500 Å, respectively. Ohmic contact stripes andislands 161, 165 a, 163 b, 1.65 b, and 167, data lines 171, a pluralityof the first drain electrodes 175 a, a plurality of the power lines 172,and the second drain electrodes 175 b are formed by etching the datametal layer and the ohmic contact layer at the same time usingphotolithography.

As shown in FIGS. 8 to 98, the passivation layer 180 is formed bycoating an organic or inorganic insulating material. A plurality of thecontact holes 181, 185, 183, 189, and 182 are formed by etching thepassivation layer 180 and gate insulating layer 140 usingphotolithography. The contact holes 181, 185, 183, 189, and 182 exposeportions of the first and second drain electrodes 175 a and 175 b andthe second gate electrode 124 b, and the ends 129 and 179 of the gateline 121 and the data line 171, respectively.

The pixel electrode 190, connecting member 192, and contact assistants81 and 82 are formed of ITO or IZO.

The partition wall 803 and auxiliary electrode 272 are formed using aphotolithography process with one mask.

The hole injection layer (not shown) formed ofpoly(3,4-ethylenedioxythiophene)-poly(styrenesulfonic acid) (PEDOT/PSS)is formed on the pixel electrode 190 surrounded by the partition wall803 using spin coating or printing.

The light emission layer 70 is formed on the hole injection layer (notshown).

The common electrode 270 is formed on the light emission layer 70.

The etch stopper type thin film transistor formed according to exemplaryembodiments of the present invention has an excellent stabilitycharacteristic as compared with an etch back type thin film transistor.This is because, when forming the etch back type thin film transistor,the amorphous silicon layer of the channel portion is partially etchedand may become damaged by an etching plasma during the etching processof the ohmic contact layer, whereas when forming the thin filmtransistor according to an exemplary embodiment of the presentinvention, the etch stop member covers the amorphous silicon layer ofthe channel portion when the data metal layer and ohmic contact layerare etched. As a result, charge mobility of the thin film transistoraccording to an exemplary embodiment of the present invention is about0.8 V/cm²sec, which is higher than the charge mobility of about 0.3V/cm²sec for the etch back type thin film transistor.

According to an exemplary embodiment of the present invention, a processof forming an etch stopper type thin film transistor can be simplifiedby forming the etch stop members using the photoresist film used in thepatterning of the amorphous silicon layer and by simultaneously etchingand patterning the ohmic contact layer and the data wire layer, therebyreducing the number of photolithography processes used to form the etchstopper type thin film transistor.

While the present invention has been described in detail with referenceto the exemplary embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A thin film transistor array panel comprising: an insulationsubstrate; gate lines formed on the insulation substrate and having gateelectrodes; a gate insulating layer formed on the gate lines;semiconductors formed on the gate insulating layer; etch stop membersformed on portions of the semiconductors; ohmic contact members formedon the etch stop members and partially contacting the semiconductors; adata wire layer formed on the ohmic contact members and havingsubstantially the same planar pattern as that of the ohmic contactmembers; a passivation layer formed on the data wire layer and havingcontact holes; and pixel electrodes formed on the passivation layer andconnected to portions of the data wire layer through the contact holes.2. The thin film transistor array panel of claim 1, wherein the datawire layer comprises: data lines that have source electrodes andintersect the gate lines; drain electrodes that are disposed on the gateelectrodes and face the source electrodes; and storage capacitorconductors that overlap the gate lines.
 3. The thin film transistorarray panel of claim 2, wherein each of the semiconductors comprises alinear portion that is formed below a corresponding data line and aprotruding portion that extends from the linear portion over acorresponding source electrode and drain electrode.
 4. The thin filmtransistor array panel of claim 3, wherein each of the etch stop memberscomprises a protruding portion that is formed on the protruding portionof a corresponding semiconductor to cover the correspondingsemiconductor located between the corresponding source electrode anddrain electrode and a linear portion that is formed on the linearportion of the corresponding semiconductor.
 5. The thin film transistorarray panel of claim 4, wherein the linear portion of the etch stopmembers is located within an area defined by sides of the linear portionof the corresponding semiconductor.
 6. The thin film transistor arraypanel of claim 4, wherein the protruding portion of the etch stopmembers is located within an area defined by sides of the protrudingportion of the corresponding semiconductor.
 7. The thin film transistorarray panel of claim 1, wherein each of the semiconductors is formed ofamorphous silicon, and each of the etch stop members is formed ofsilicon nitride.
 8. A method of manufacturing a thin film transistorarray panel, comprising: forming gate lines including gate electrodes onan insulation substrate; forming a gate insulating layer, asemiconductor layer, and an etch stop layer on the gate lines; etchingand patterning the etch stop layer and the semiconductor layer at thesame time using photolithography; ashing and partially removing aphotoresist film pattern used in the etching and patterning of the etchstop layer and the semiconductor layer; etching the etch stop layerexposed by removed portions of the photoresist film pattern to form etchstop members; depositing an ohmic contact layer and a data metal layeronto the etch stop members; etching the ohmic contact layer and the datametal layer at the same time using photolithography to form data lineshaving source electrodes, drain electrodes facing the source electrodes,and ohmic contact members below the source electrodes and the drainelectrodes; forming a passivation layer on the data lines and the drainelectrodes; and forming pixel electrodes on the passivation layer. 9.The method of claim 8, wherein each of the ohmic contact members hassubstantially the same planar pattern as that of a data line and drainelectrode formed thereon.
 10. The method of claim 8, further comprising:connecting the pixel electrodes to the drain electrodes.
 11. The methodof claim 8, wherein the gate insulating layer, semiconductor layer, andetch stop layer are sequentially formed on the gate lines.
 12. A thinfilm transistor array panel comprising: an insulation substrate; gatelines that are formed on the insulation substrate and that have firstgate electrodes; second gate electrodes and storage electrodes that areformed on the insulation substrate; a gate insulating layer that isformed on the gate lines, the second gate electrodes, and the storageelectrodes; first and second semiconductors that are formed on the gateinsulating layer; first and second etch stop members that are formed onportions of the first and second semiconductors, respectively; ohmiccontact members that are formed on the first and second etch stopmembers and that partially contact the first and second semiconductors;a data wire layer that is formed on the ohmic contact members and thathas substantially the same planar pattern as that of the ohmic contactmembers; a passivation layer that is formed on the data wire layer andthat has a plurality of contact holes; and pixel electrodes that areformed on the passivation layer and that are connected to portions ofthe data wire layer through the contact holes.
 13. The thin filmtransistor array panel of claim 12, wherein the data wire layercomprises: data lines that have first source electrodes and intersectthe gate lines; first drain electrodes that are disposed on the firstgate electrodes and face the first source electrodes; power lines thathave second source electrodes and intersect the gate lines; and seconddrain electrodes that are disposed on the second gate electrodes andface the second source electrodes, wherein the thin film transistorarray panel further comprises connecting members that electricallyconnect the first drain electrodes and the second gate electrodes toeach other.
 14. The thin film transistor array panel of claim 13,wherein each of the first semiconductors has a linear portion that isformed below a corresponding data line, and a first channel portion thatextends from the linear portion over a corresponding first source electrode and first drain electrode, each of the second semiconductors has astorage electrode portion that overlaps a corresponding storageelectrode, and a second channel portion that extends over acorresponding second source electrode and second drain electrode, eachof the first etch stop members covers the first semiconductor betweenthe corresponding first source electrode and first drain electrode, andeach of the second etch stop members covers the second semiconductorbetween the corresponding second source electrode and second drainelectrode.
 15. The thin film transistor array panel of claim 14, whereinthe first and second semiconductors are formed of amorphous silicon, andthe first and second etch stop members are formed of silicon nitride.16. The thin film transistor array panel of claim 14, furthercomprising: partition walls that are formed on the pixel electrodes; alight emission layer that fills frames defined by the partition walls;and a common electrode that is formed on the light emission layer.
 17. Amethod of manufacturing a thin film, transistor array panel, comprising:forming gate lines having first gate electrodes, second gate electrodes,and storage electrodes on an insulation substrate; forming a gateinsulating layer, a semiconductor layer, and an etch stop layer on thegate lines, the second gate electrodes, and the storage electrodes;etching and patterning the etch stop layer and the semiconductor layerat the same time using photolithography; ashing and partially removing aphotoresist film pattern used in the etching and patterning of the etchstop layer and the semiconductor layer; etching the etch stop layerexposed by removed portions of the photoresist film pattern to formfirst and second etch stop members; depositing an ohmic contact layerand a data metal layer onto the first and second etch stop members;etching the ohmic contact layer and data metal layer at the same timeusing photolithography to form data lines having first sourceelectrodes, drain electrodes facing the first source electrodes, powerlines having second source electrodes, second drain electrodes facingthe second source electrodes, and ohmic contact members below the firstand second drain electrodes; forming a passivation layer on the datalines, the first drain electrodes, the power lines, and the second drainelectrodes; and forming on the passivation layer pixel electrodes thatare connected to the second drain electrodes and connecting members thatelectrically connect the first drain electrodes and second gateelectrodes to each other.
 18. The method of claim 17, wherein each ofthe ohmic contact members has substantially the same planar pattern asthat of a data line, first drain electrode, power line, and second drainelectrode formed thereon.
 19. The method of claim 17, furthercomprising: forming partition walls on the pixel electrodes; forming anorganic fight emission layer that fills frames defined by the partitionwalls; and forming a common electrode on the organic light emissionlayer.
 20. The method of claim 17, wherein the gate insulating layer,semiconductor layer, and etch stop layer are sequentially formed on thegate lines, the second gate electrodes, and the storage electrodes.